Multiple choice A matched CMOS static inverter has (W/L)of the PMOST 1. Equal (W/L). 2. Smaller than (W/L). 3. Larger than (W/L). 4. Equal the inverse of (W/L). The delay of a single stage in a ring oscillator formed of 57 stages oscillating at 100 MHz is equal to a. 1.75 us b. 0.57 us c. 87.7 ps d. 57 ns Charge leakage and charge sharing in dynamic CMOS gates: 1. Ensure Vow equals VDD 2. Reduces Vou to Vpp – V 3. Have reduced effect at higher fclock 4. Ensure Vot equals zero In short channel MOSFET's the threshold voltage 1. Is independent of VDs 2. increases with increasing Vos 3. decreases with increasing Vps 4. is larger than in large channel MOSFET's The numbers of entry bits m to the row address decoder and entry bits n to the column Charge akage and charge sharing in dynamic CMOS 1. Ene Vaals Ve 2. Rew V V 3. Haverede effect her 4. Fare Votequals zero -V In short channel MOSFET the threshold voltage 1. hs independent of 2. increases with increasing V 3.des with increasing V 4 is larger than in large channel MOSFET'S The names of this to the row ess dender and try ess dederina 512 MB can be equal to to the column w 2m 1 and Compared to long che devices in the c The on current is el MOS trans The Threshold voltage is c. The carrier mobility in the channel is iv. equalled holes d. The MOSFET current e s at a smaller drain voltage due to Pinch of ii. Velocity iii. High chun resistance iv. Very low channel resistance . The drain and source series resistance are More important iile important In qually important . The electron velocity in the channel is I.modendent on the electrice ii. less dependent on the electric field directly open to the clefield equal to the holely Afer reading the stored it in a dynamic memory the information is Destroyed Toggled changed to i None of the above mplement 2. Ina NOR ROM, the presence of an NMOS riord es represents SKONAL TO CLOCK None of the above Whendinga od ZERO hit the NOR mut ROM chaves like Is programed the manufacturer Is programe in the field access memory 5. The www address devederis necessary in and 1. activate the bit line the word in 4. None of the above 6. The dynamic memory cell includes 1 Two MOST and one capacitor 2. One MOST and one capacitor 3. One MOST and two capacitors in parallel 4. None of the above 7. Transmission gate have 1. A good ZERO and a bad ONE 2. A good ONE and a bad ZERO 3. A Bad ZERO and Ahad ONE 4. None of the above 8. Dynamo CMOS logic helps resolving the problem of Bad HIGH level in cascaded inverters 2. Bad Low level in cascaded inverters 3. Static power in cascaded inverters 4. None of the above 9. Charge sharing in dynamic logic leads to 1. Bad LOW level 2. Bad HIGH level 3. Good HIGH level 4. Static power 10. The advantage of PSEUDONMOS compared to CMOS galesis in its 1. Lower Static power 2. Good LOW level 3. Higher Fan-in 4. None of the above At static input states, the static power in a combinational CMOS digital gale: 1. Depends on the number of NMOS and PMOS transistors 2. Depends on the function implemented by the circuit 3. Equals zero 4. Mainly depends on the value of the supply Voe Increasing the number of series NMOS transistors in CMOS digital gates result 1. Longer propagation delay 3. Does not affect the propagation delay resistance 2. Shorter propagation delay 4. Decreases the pull down In CMOS Transmission gates The NMOST is ON when the PMOST IS OFF 2. The PMOST is ON when the NMOST is OFF 3. The NMOST PMOS are ON together or OFF together 4. None of the above With decreasing channel length, the threshold voltage of short channel MOSFET'S 1. decreases 2. increases 3. not affected 4. changes sign Electron velocity saturation in short channel MOSFETS 1. is an advantage 2. Results in reduced delay 3. shifts saturation de toamaller voltage results in smaller drain current


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